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UG Series
0.6m ULC Series
Description
The UG series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.6-m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 350 MHz, operating clock frequencies up to 150 MHz and input to output delays as fast as 5 ns. The architecture of the UG series allows for efficient conversion of many PLD architectures and FPGA device types. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing. Conversion to the UG series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100 mA or more even when not being clocked. The UG series has a very low standby consumption of 0.4 nA/gate typically, which would yield a standby current of 4 mA on a 10,000 gate design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared. The UG series provides several options for output buffers, including a variety of drive levels up to 24 mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available as required. The UG series is designed to allow conversions of high performance 3.3V devices as well as 5.0V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption.
Features
D High performance ULC family suitable for medium- to large-sized CPLDs and FPGAs D Conversions to over 200,000 FPGA gates D Pin counts to over 300 pins D Any pin-out matched due to limited number of dedicated pads D Advanced 0.6-m (drawn)/0.45-m (effective) feature size D Triple-layer or dual-layer metal CMOS technology D High speed performance: - 250-ps typical cell delay - 350-MHz toggle rate D Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, PGA/PPGA D 3.3V and/or 5.0V operation. D Low quiescent current: 0.4 nA/gate D Available in commercial, industrial, automotive, military and space grades.
Rev. B
- 25 May. 98
5-1
UG Series
Product Outline
Part Number
UG01 UG04 UG09 UG14 UG20 UG33 UG42 UG52 UG70 UG90 UG120 UG140
Full programmables Pads
30 48 72 88 104 130 146 162 188 212 244 264
Equivalent FPGA Gates
3300 7500 15800 24300 34800 46000 58600 63700 85800 108500 145100 156800
Maximum Drive
N/A 310 790 1210 1740 2880 3660 4550 6130 7750 10360 12250
Architecture
The basic element of the UG family is called a cell. One cell can typically implement between two to three FPGA gates. Cells are located contiguously through out the core of the device, with routing resources provided in two or three metal layers above the cells. Some cell blockage does occur due to routing, and utilization will be significantly greater with three metal routing than two. The sizes listed in the Product Outline are estimated usable amounts using three metal layers. I/O cells are provided at each pad, and may be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or PLD pinout. Special function cells and pins are located in the corners which typically are unused. In order to improve noise immunity within the device, separate VDD and VSS busses are provided for the internal cells and the I/O cells.
Slew Rate Controlled Output Buffer In this mode, the p- and n-output transistor commands are delayed, so that they are never set "ON" simultaneously, resulting in a low switching current and low noise. These buffer are dedicated to very high load drive.
3.3V Compatibility
The UG series of ULCs is fully capable of supporting high-performance operation at 3.3V or 5.0V. The performance specifications of any given ULC design however, must be explicitly specified as 3.3V, 5.0V or both.
Power Supply and Noise Protection
In order to improve the noise immunity of the UG series, several mechanisms have been implemented inside the UG devices. Two kinds of protection have been added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the core. I/O buffers switching protection Three features are implemented to limit the noise generated by the switching current: The power supplies of the input and output buffer are separated. The rise and fall times of the output buffers can be controlled. The number of buffers that are connected on the same power supply line is limited.
I/O Options
Inputs Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull up or pull down resistor. Fast Output Buffer Fast output buffers are able to source or sink 3 to 12 mA according to the chosen option. 24mA achievable, using 2 pads.
5-2
Rev. B
- 25 May. 98
UG Series
Core switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: Some decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution lessens the parasitic elements such as inductance and resistance and constitutes an artificial VDD and VSS plane. One mesh of the network supplies approximately 150 cells. A low-pass filter has been added between the core and the inputs of the output buffers. This limits the transmission of the noise coming from the ground or the VDD supply of the core via the output buffers.
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7.0 V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 7.0 V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150_C
Recommended Operating Range
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V "5% or 3.3 V "5% Operating Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85_C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125_C
DC Characteristics
Parameter Symbol
VOH VOL VIH VIL VIN = VSS Input Leakage Current IIX VIN = VDD VIN = VSS, with pull-up VIN = VDD, with pull-down Output Leakage Current Output Short Circuit Current Standby Current Operating Current Input Capacitance Output Capacitance IOZ IOS ICCSB IDDOP CIN COUT VDD = 5.0 V, VIN = 2.0 V VOUT = 2.0 V VOUT = VSS or VDD VOUT = VDD VOUT = VSS VDD = 5.25 V, VIN = VSS -130 -5 -100 -5 -1 1 -40 40 "1 90 -60 0.4 0.3 2.5 2 pF 1 0.4 100 5 160 mA nA/Gate 5
Base Part
TA = Commercial IOH = 24, 12, 6, 3 depending on buffer IOL = -24, -12, -6, -3 depending on buffer
Min
2.4
Typ
Max
Unit
Output Voltage
0.4 2.0 0.8 V
Input Voltage
A
A/Gate/
MHz
Notes: a. IOH = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements.
Rev. B
- 25 May. 98
5-3
UG Series
Internal Timing Characteristics
These timing parameters for selected macro cells are provided for information only. Only pin-to-pin timing characteristics are guaranteed for ULCs, and the actual specification is determined by the original FPGA or PLD data sheet plus any specific parameters that are agreed to separately by Atmel Wireless & Microcontrollers.
Conditions: VDD = 5 V, Typical Process, Statistical Wire Length. All delays measured at VIN/VOUT = 2.5 V.
Macro Type
2-Input NAND 4-Input NAND Inverter Inverting Tri-State Buffer NAND2 NAND4 INV TRISTAN Propagation Time tPD
Parameter
Symbol
Min
Maxa
0.39 0.68 0.41 0.74
Maxb
0.56 0.88 0.68 0.99 0.97
Units
ns
Enable Time Setup Time Hold Time Pulse Width
tEN tSU tH tPW tDQ tEN tRN tSU tH tPW tCQ tRN tPLH tPHL tPLH 0.40 0.00 0.60 0.60 0.00
0.69
Resetable Latch
LATCHR
Propagation Time Enable Time Reset Time Setup Time Hold Time
0.97 1.22 0.87
1.25 1.49 1.10
D Flip-Flop with Reset
FDFFR
Pulse Width Clock Delay Time Reset Time
0.95 0.81 0.80 0.68 0.80 0.68 2.97 1.96 2.49 1.74 3.27 1.60 2.49 1.74 3.27 1.60
1.22 0.94 0.95 0.74 0.95 0.74 8.18 4.23 6.42 3.47 7.17 3.30 6.42 3.47 7.17 3.30 ns
TTL Compatible Input Buffer TTL Compatible I/O Buffer Input Mode Output Buffer
BUFINTTL
BIOT12 Propagation Time BOUT6
tPHL tPLH tPHL tPLH
TTL Compatible I/O Buffer
BIOT12 Enable Time
tPLH tPZH tPZL tPLH tPHL tPZH tPZL
Propagation Time Tri-State Output Buffer B3STA12 Enable Time
Notes a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of BOUT6 is 20 pF, BIOT12 and B3STA12 are 30 pF. b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer. Loading of BOUT6 is 80 pF, BIOT12 and B3STA12 are 120 pF.
5-4
Rev. B
- 25 May. 98
UG Series
Derating Factors: tP = KP x Kt x KV x tNOMINAL Process
Process KP Best 0.82 Nominal 1.00 Worst 1.28
Ambient Temperature _C
TA KT -55 0.74 -40 0.79 0 0.92 25 1.00 70 1.15 85 1.20 125 1.32
Supply Voltage
VDD KV 2.7 1.89 3 1.66 3.13 1.58 3.3 1.49 3.47 1.41 3.6 1.35 4 1.23 4.5 1.1 4.75 1.05 5 1 5.25 0.96 5.5 0.93
External Timing Characteristics
(Over the Operating Range)
These timing parameters are provided for information only. Actual pin-to-pin timing characteristics
guaranteed for ULCs are determined by the original FPGA or PLD data sheet plus any specific parameters that are agreed to separately by Atmel Wireless & Microcontrollers.
Max Parameter Symbol Base Part
UG01 UG04-UG09 Propagation Time tPD UG14-UG20 UG33-UG90 UG120-UG140 UG01 UG04-UG09 Clock Delay Time tCO UG14-UG20 UG33-UG90 UG120-UG140 Hold Time tH UG01 UG04-UG09 Output Enable Time tEN UG14-UG20 UG33-UG90 UG120-UG140 32 50 100 220 300 32 50 100 220 300 0.0 6.5 7.5 8.5 10.0 11.0 10.0 11.5 13.0 15.0 16.5
SSO
Min Typ
5.0 6.0 7.0 8.5 9.5 6.5 7.5 8.5 10.0 11.0
Unit Max
7.5 9.0 10.5 13.0 14.5 10.0 11.5 13.0 15.0 16.5 ns
Rev. B
- 25 May. 98
5-5
UG Series
Power Consumption
Static Power Consumption for UG Series ULCs
There are three main factors to consider: - Leakage in the core: - PLC = VDD * ICCSB * number of used gates - Leakage in inputs and tri-stated outputs: - PLIO = VDD * (IIX * N + IOZ * M) - where: N = number of inputs - M = number of tri-stated outputs - Care must be taken to include the appropriate figure for pins with pull-ups or pull-downs. In practice, the static consumption calculation is typically done to determine the standby current of a device; in this case only those pins sourcing current should be included, i.e. where VIN or VOUT = VDD. - Dc power dissipation in driving I/O buffers due to resistive loads: - In practice, the static consumption calculation is typically done to determine the standby current of a device, and under circumstances where all of the outputs are tri-stated or in input mode. So this term is zero. - Global formula for static consumption: - PSB = PLC + PLIO approximated as purely capacitive loads, allowing this term to be treated as zero. TTL loads source significant current in the low state, but not the high state, allowing the second summation to be ignored. If a 50% duty cycle is assumed for dynamic outputs driving TTL loads, this can be approximated as: - P1 (mW) = VOL * (n * IOLn/2 + m * IOLm) (TTL loads) - where n are dynamic outputs and m are static low outputs. - Dynamic power dissipation for the internal gates: - P2 (mW) = VDD * IDDOP * g (Nf * fg)/1000 - where: Nf = number of gates toggling at frequency fg - fg = clock frequency of internal logic in MHz - Note: If the actual toggle rates are not known, a rule of thumb is to assume that the average used gate is toggling at one half of the input clock frequency. - Dynamic power dissipation in the outputs: - P3 (mW) = VDD2 * n fn * (COUT + Cn)/1000 - where: fn = clocking frequency in MHz of output n - Cn = output load capacitance in pF of output n - COUT = output capacitance from DC Characteristics - Global formula for dynamic consumption: - P = P1 + P2 + P3 Example: Static calculation - A 100-pin ULC with 3000 used gates, 10 inputs, 20 I/Os in input mode, 40 outputs all tri-stated. No pull-ups or pull-downs. Half of the pins are at VDD, half at VSS. Input clock is not toggling. For this example only the current calculation is desired, so the VDD term in the equations is dropped. - PLC = 1 * 3000 = 3 mA - PLIO = ((10 + 20) * 5 + 40 * 5)/2 = 105 mA - PSB = 3 + 105 = 108 mA Dynamic Calculation - We take a 16-bit resettable ripple counter which is approximately 100 gates, operating at a clock frequency of 33 MHz, which gives an average clock frequency of 33 MHz/16 for each bit and each output. There are no static outputs on this device. Operation is at 5 V, and 6-mA outputs are used and loaded at 25 pF. The output buffers are driving CMOS loads. Rev. B
Dynamic Power Consumption for UG Series ULCs
There are four main factors to consider: - Static power dissipation is negligible compared to dynamic and can be ignored. - Dc power dissipation in I/O buffers due to resistive loads: - P1 (mW) = VOL * n (DLn * IOLn) + ( VDD - VOH) * n (DHn * IOHn) - where: n is a summation over all of the outputs and I/Os. - IOLn and IOHn are the appropriate values for driver n - DLn = percentage of time n is being driven to VOL - DHn = percentage of time n is being driven to VOH - It is difficult to obtain an exact value for this factor, since it is determined primarily by external system parameters. However, in practice this can be simplified to one of two cases where the device is either driving CMOS loads or driving TTL loads. CMOS loads can be 5-6
- 25 May. 98
UG Series
- - - - P1 = 0 P2 = 5 * 0.5 * 100 * 33/16/1000 = 0.5 mW P3 = 52 * 16 * 33/16 * (25 + 2)/1000 = 22 mW P = 0 + 0.5 + 22 = 22.5 mW D Transient energy is absorbed at the end of the line to prevent reflections which would lead to inaccurate ATE measurements. Figure 5. Typical ULC Test Conditions
Typical ULC Test Conditions
For AC specification purposes, an improved output loading scheme has been defined for Atmel Wireless & Microcontrollers high-drive (24 mA), high-speed ULC devices. The schematic below (Figure 5.) describes the typical conditions for testing these ULC devices, using the standard loading scheme commonly available on high-end ATE. Compared to a no-load condition, this provides the following advantages: D Output load is more representative of "real life" conditions during transitions.
12 mA
D.U.T.
1.5 V 12 mA Comp
Rev. B
- 25 May. 98
5-7

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